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NCP5080 Xenon Photoflash Capacitor Charge with Photo Sense Interface
The NCP5080 product is a high voltage boost driver dedicated to the Xenon power flashes. The built-in DC/DC converter is based on a flyback structure with an external transformer to adapt any range of high voltage demand. The external feedback network makes it possible to dynamically adjust of the output voltage.
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Features
* * * * * * * *
2.7 V to 5.5 V Input Voltage Range Xenon Function Fully Supported Built-in Short Circuit Protection Dedicated Photo Flash Trigger Pin Provides IGBT drive Embedded Photodiode Sense Adjustable Primary Ipeak Current This is a Pb-Free Device
LLGA12 CASE 513AD A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) PHREF TRGFL IGBT VBAT PGND VSW 1 2 3 4 5 6 12 11 10 9 8 7 PHSEN VHB IPKRF AGND READY EN
Typical Applications
* Digital Camera Photo Flash * Digital Cellular Phone Camera Photo Flash * Low Power Beacon
ORDERING INFORMATION
Device NCP5080MUTXG Package LLGA12 (Pb-Free) Shipping 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
+VBAT GND GND R6 1k +VBAT S2 GND +VBAT ENABLE S1 TRGFL TRIGGER 12 GND 10 9 IPK-REF AGNG NCP5080 R1 GND GND C1 10nF 12k R2 VHT 3.0M 76 5 GND 8 IGBT VFB 3 11 33R 134 G Collector Emitter Q1 IGBT-CY25BAH-8F GND D6 U1 READY EN READY 8 7 2 1 READY EN 1 TRGFL PHREF PHSEN Vsw PGND 6 GND 5 R7 10k COILCRAFT-CJ5143-AL R12 2 3 GND VBAT 4 2 T1 4 BAS21-B XENON TUBE X1 1 220k T2 FLTRG-TB-KR8 3 C4 1 Np 47nF/400V C2 10mF/6.3V 1 D1 4 VHT C3 22mF/315V R3
3 Ns
2
11k
(c) Semiconductor Components Industries, LLC, 2007
R5
Figure 1. Typical NCP5080 Photo Flash Application
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July, 2007 - Rev. 1
Publication Order Number: NCP5080/D
NCP5080
+VBAT VBAT 4 6 Vsw Q1
UVLO
Thermal Shutdown Boost Driver +Vbat
5 READY 8 GND Vbat EN TRGFL PHREF PHSEN IPKREF AGND 7 2 100k 1 100k 12 10 9 GND Controller GND GND GND Buffer GND 11 3
PGND
IGBT
VFB
Figure 2. NCP5080 Simplified Block Diagram
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NCP5080
PIN DESCRIPTIONS
PIN 1 Name PHREF Type INPUT, ANALOG Description The external controller biases this pin with the reference voltage used, together with the PHSEN pin, to control the illumination of the photo scene. The VPH voltage shall be in the 0.5 V to 1.5 V range, capable to support the internal resistor network (R load minimum is 500 kW). The photo sense function is deactivated when 0.5 V v PHREF v 1.5 V and PHSEN = GND (see Table 4). A positive going pulse applied to this pin triggers the external IGBT and the flash sequence takes place. This command is active when EN = High, but is not synchronized with the output voltage value (see Table 4). This pin provides the signal to drive the external IGBT and can be forced High or Low independ ently of the output voltage value, (assuming EN = High) according to the TRGFL pin status (see Table 4). Depending upon the type of IGBT used in the application, specific external gate network might be necessary to satisfy the IGBT gate drive conditions. This pin carries the power supply to the analog, digital and DC/DC converter blocks and must be decoupled to ground by a 10 mF ceramic capacitor connected as close as possible to the package. This pin is the GROUND return for the DC/DC converter and must be connected to the system ground, a ground plane is strongly recommended. This pin is the drain of the internal NMOS device and shall be connected to the primary of the external transformer. Care must be observed, at PCB layout level, to minimize the noise due to the large current and voltage transients present on that pin during normal operation. This pin controls the operation of the boost converter: EN = Low The DC/DC converter is OFF, no flash can take place, the voltage across the external reservoir capacitor depends solely upon the leakage current present in the environment. EN = High The DC/DC converter is activated, the voltage across the external reservoir capacitor is regulated at the predetermined value according to the VFB reference. Similarly, a flash can take place, assuming the Xenon tube is properly biased. This Open Drain Output goes LOW when the output voltage has reached the predetermined value across the external reservoir capacitor. The signal is HIGH when Vout is below the expected value, or if a fault has been detected at chip level. This pin returns the Analog and Digital blocks ground and must be connected to the external ground plane. This pin provides the setup of the peak current flowing into the primary of the external transformer. The main purpose of this reference is to adjust the size of the transformer as a function of the flash power. This pin is the voltage feedback used to regulate the high voltage across the external reservoir capacitor. The impedance across VFB and GND shall be kept to the lowest possible value to minimize the noise pickup. This pin provides a feedback from the illumination during the photo flash and, associated to the PHREF signal, controls the duration of the photo flash. The photodiode, connected across PHSEN and VBAT, shall be adjusted according to the Xenon flash in use. On the other hand, an external pulldown resistor shall be connected between the PHSEN pin and the ground reference. Such a resistor shall be calculated to cope with the type of photodiode used in the illumination sense loop. The photo sense function is deactivated when PHSEN = GND and 0.5 V v PHREF v 1.5 V (see Table 4).
2
TRGFL
INPUT, DIGITAL OUTPUT, POWER
3
IGBT
4 5 6
VBAT PGND VSW
INPUT, POWER POWER OUTPUT, POWER INPUT, DIGITAL
7
EN
8
READY
OUTPUT, DIGITAL POWER INPUT, ANALOG INPUT, ANALOG INPUT, ANALOG
9 10
AGND IPKREF
11
VFB
12
PHSEN
1. Using low ESR ceramic capacitor, X5R type, is mandatory to optimize the DC/DC operation and to reduce the EMI.
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MAXIMUM RATINGS (Note 2)
Symbol VBAT, VCC VSW EN, PFLASH ESD Power Supply Output Power Supply Digital Input Voltage Digital Input Current Human Body Model: R=1500 W, C=100 pF (Note 3) Machine Model LLGA12 package Power Dissipation @ TA = +85C (Note 4) Thermal Resistance Junction-to-Air Thermal Resistance Junction-to-Case Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Latchup Current Maximum Rating per JEDEC Standard: JESD78 Rating Value -0.3 < VBAT < 7.0 40.0 -0.3 < V < VBAT 1 2 200 400 100 12 -40 to +85 -40 to +125 +150 -65 to + 150 $100 Unit V V V mA kV V mW C/W C/W C C C C mA
PD RTHja RTHJC TA TJ TJmax Tstg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum electrical ratings define the values beyond which permanent damage(s) may occur internally to the chip whatever be the operating temperature 3. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) $2.0 kV per JEDEC standard: JESD22-A114 Machine Model (MM) $200 V per JEDEC standard: JESD22-A115 4. The maximum package power dissipation limit must not be exceeded. 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020A.
POWER SUPPLY SECTION (Typical values are referenced to TA =+25C, minimum and maximum values are referenced -40C to +85C ambient temperature, unless otherwise noted, and operating conditions are 2.85 V < VBAT < 5.5 V, unless otherwise noted)
Pin 4 4 6 6 Symbol VBAT UVLO Ipk Idss tstart 4 Istdb Rating DC/DC Converter Power Supply Input Voltage Undervoltage Monitoring Primary Transformer Peak Current (750 mA Final Test Correlation) Ripk = 11 kW Internal Power Switch NMOS Leakage Current @ Vdss = 40 V DC/DC Start Time (Cout = 100 mF, No Load) VBAT = 4 V, from EN Positive Pulse to Vout = 300 V (Note 6) Standby Current, VBAT = 5.5 V, Iout = 0 mA, EN = Low VBAT = 3.6 V, Iout = 0 mA, EN = Low Operating Current, @Vout = Nominal, VBAT = 3.6 V, EN = High External IGBT Drive @ VBAT = 3.6V Vgs = High (Note 8) Vgs = Low Maximum Inductor Charge Current ON Time Maximum Inductor Discharge Current OFF Time Leading Blanking (Note 7) Internal Power Switch NMOS RDS(on) @ VBAT = 4.2 V 0.5 W 23 33 60 60 260 250 600 37 52 ms ms ns mW 2 Min 2.7 2.1 Typ Max 5.5 2.6 1.5 mA 0.5 s 3 mA 1 0.75 mA Unit V V A
4 3
Iop Rdrv
Tonmx Toffmx TLEB 6 RDS(on)
6. Since this parameter is highly depending upon the application, it is not tested, guaranteed by design. 7. The blanking parameter is internal and cannot be tested in production, guaranteed by design. 8. Since the IGBT gate drive is derived from the VBAT supply, special care must be taken to ensure that the IGBT triggers when Vgs is high and VBAT is below 3.0 V.
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NCP5080
ANALOG SECTION (Typical values are referenced to TA = +25C, minimum and maximum values are referenced -40C to +85C ambient temperature, unless otherwise noted, operating conditions 2.85 V < VBAT < 5.5 V, unless otherwise noted)
Pin 10 10 10 6 Symbol IREF VREF IPKR FPWM Rating Reference current @ VREF = 1.14 V (Notes 9 and 10) Reference Voltage (Note 10) Reference Current (IREF) Current Ratio Internal DC/DC Flyback Frequency @ VBAT = 4.2 V, Ip = 1 A, Lp = 6 mH, Lf = 200 nH, Transformer = TDK (Note 11) Output Voltage Feed Back reference Photo Sense Voltage Reference Photo Reference Internal Resistance (Pin 1 to GND) Photo Feedback Tolerance Min 10 -3% 12000 15 1.14 13700 Typ Max 100 +3% 15400 600 kHz Unit mA V
11 1 1
VFB VPH VPHR PFB
1.10 0.5
1.15
1.20 1.5
V V kW %
625 $3
9. IREF current specifies the reference current range one can absorb from the IREF pin 10. The external circuit must not force the IREF pin voltage either higher or lower than the 1.14 V specified. 11. This parameter depends solely upon the output transformer and load characteristic and cannot be tested. 12. The overall photo sense tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended.
DIGITAL PARAMETERS SECTION (Typical values are referenced to TA = +25C, minimum and maximum values are referenced -40 C to +85C ambient temperature, unless otherwise noted, operating conditions 2.85 V < VBAT < 5.5 V, unless otherwise noted)
Pin 2, 7 2, 7 8 2 2, 7 NOTE: Symbol VIH VIL VOL Tpwfl Rp Rating EN, TRGFL Input Digital Signal EN, TRGFL Input Digital Signal Ready Output Digital @ Irdy = 1 mA TRGFL Input Flash Signal Pulse Width EN, TRGFL Input Pulldown Resistor 10 50 100 200 Min 1.2 0 Typ Max VBAT 0.4 0.3 Unit V V V ms kW
Digital inputs undershoot v 0.30 V to ground, Digital inputs overshoot < 0.30 V to VBAT. DC/DC Startup EN DC/DC Operation Start Next Cycle
Vout Reference
Vout READY TRGFL Vout = Programmed Value Send Flash Command
Figure 3. Basic Operation Timings DC/DC Operation
The converter is based on a flyback topology, associated to an external transformer dedicated to the high voltage application. The Primary/Secondary turns ratio is defined to
limit the peak voltage, at the NCP5080 pin VSW level, to the operating voltage sustained by the internal NMOS device. With a 1:10 ratio, the peak voltage is limited to 30 V to
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NCP5080
supply a regulated 300 V across the external reservoir capacitor. Note that although an OVP circuit is built-in the NCP5080 chip, it is strongly recommended to avoid operation without an external reservoir capacitor, a 1 mF / 315 V being the minimum value. When the NMOS is ON, the current increases into the primary of the transformer until either the Ipeak limit has been reached, or the time out is finished: at this point, the NMOS is switched OFF and the energy stored into the primary is dumped to the secondary, providing the current to recharge the reservoir capacitor. The OFF period is monitored by sensing the primary voltage and the system will re-start a new cycle when either Vp = 0 V or the time out is finished. The external resistor divider, connected across Vout and Ground, senses the output voltage to close the feedback loop at FBD pin. The output voltage is based on the 1.2 V reference and the R1/R2 ratio: Vout = VREF * ((R1 + R2) / R2). The output voltage is regulated when the EN = H, but drops to zero when EN = L. In this case, the discharge time of the external reservoir depends solely upon the value of the passive component and the leakage currents that might exist at system level. The DC/DC converter is switched OFF when either EN = Low, or TRGFL = High, or when the output voltage has reached the programmed value (see Figure 3).
Inductor Peak Current
In order to provide more flexibility to the NCP5080 driver, an extra pin, IPKREF, is provided to set up the peak current flowing into the primary inductor of the transformer. The IREF is given by the 1.14 V voltage reference and the value of the external resistor:
I REF + 1.14 V RIPK
(eq. 1)
The primary peak current is given by Equation 1:
I peak + I REF * 14000
(eq. 2)
The maximum Ipeak current shall be limited to 1.5 A maximum, assuming the transformer is sized to sustain such amount of electromagnetic energy. The efficiency of the DC/DC converter, and the recharge cycle time as well, depends upon the ESR and leakage inductance of the power transformer: a poor transformer will generate large oscillations during the operation which will be difficult to filter out at PCB level.
Table 1. PREFERRED POWER TRANSFORMER MANUFACTURERS
Manufacturer TDK Coilcraft Model LDT565620ST-20 3 CJ5143-AL Comments Ipeak = 750 mA Max Ipeak = 1200 mA Max
Table 2. PREFERRED HIGH VOLTAGE TRIGGER FUNCTION
Component High Voltage Trigger High Voltage Ceramic Capacitor 22 mF/330 V to 120 mF/330 V Manufacturer PCA TDK RUBYCON Model EPC3215G-X C3225X7R2J473M FW series Vout = 4000 V Reference design+ Preferred Comments
Table 3. PREFERRED XENON LAMP
Component Flash Lamp-Reflector Assembly Flash Lamp-Reflector Assembly Flash Lamp-Reflector Assembly Flash Lamp-Reflector Assembly Manufacturer Perkin-Elmer Perkin-Elmer Nam Kwong Co. LTD. Nam Kwong Co. LTD. Model RF-ASYRF160709 PKI08 (H) RF-ASY RF160709 PKI07 (H) FET-O-D03150220E-02 FET-O-D02230202A-07 Comments Ej = 1.5 Joule Cout = 33 mF Ej = 2.1 Joule Cout = 47 mF 9.8 Joule, Cout = 180 mF 8.0 Joule, Cout = 150 mF
Perkin Elmer coordinates: kimguan.lim@perkinelmer.com Flash Strobe
The flash is activated by the digital status present at the TRGFL Pin and the logic condition of the EN and PHSEN Pins as defined in Table 4.
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NCP5080
Table 4. FLASH OPERATING TRUE TABLE
EN 0 1 1 TRGFL X 0 1 PHREF X 0.5 V to 1.5 V 0.5 V to 1.5 V PHSEN X GND GND Status System Disabled: The boost and the flash are de-activated. Any on going flash is immediately switched OFF. System Active: The output reservoir is being charged and the output voltage regulated. The photo sense is deactivated. The IGBT gate drive is LOW. System Active: The output reservoir is being charged and the output voltage regulated. The photo sense is deactivated. The IGBT gate drive is HIGH whatever be the Vout voltage value . The xenon tube is fired if Vout = Vxen minim um and the flash light keeps going until either TRGFL = 0, or the reservoir capacitor is fully discharged. System Active: The output reservoir is being charged and the output voltage regulated. The photo sense is activated . The IGBT gate drive is LOW. System Active: The output reservoir is being charged and the output voltage regulated. The photo sense is deactivated and the flash is switched OFF if the voltage present at the PHSEN Pin is higher the reference voltage applied to the PHREF Pin. The IGBT gate drive is HIGH whatever be the Vout voltage value . The Xenon tube is fired if Vout = Vxen minimum and the IGBT keeps going until either TRGFL = 0, or the PHSEN > PHREF, or the reservoir capacitor is fully discharged.
1 1
0 VREF 1 VREF PHOTODIODE PHOTODIODE
The TRGFL signal provides a simple way to generate multiple consecutive flashes (similar to the stroboscope effect) to minimize the red eye effect, or to freeze multiple pictures of moving objects. The IGBT must be capable to turn ON with limited Gate voltage.
Photodiode Sensor
The photodiode sensor provides a feedback from the illumination generated by the xenon flash to avoid the overexposed picture. The PHREF pin shall be biased according to the model of xenon tube (in particular, the energy level) and optical lens aperture.
Table 5. NCP5080 PHOTO SENSE TRUE TABLE
Pin 0.5 V v PHREF w 1.5 V PHSEN = GND PHREF = VPH PHSEN = Photodiode Operation Photodiode Sense Deactivated Photodiode Sense Activated
The function can be deactivated when not used in the application shown in Table 5. More over, connecting the PHREF Pin to the IPKREF Pin provides an easy way to fully disconnect the photo sense function. The external photo sense element shall be connected across PHSEN and VBAT to source the current as the illumination increases, with a pull-down resistor connected to the ground reference as depicted in Figure 4. The sense resistor is calculated to get the collector current when the photo diode is saturated. With a typical 10 mA to 30 mA of photodiode current, the resistor will be 100 kW to cope with the low input battery supply voltage situation.
Operation The IGBT is solely controlled by the TRGFL Pin The IGBT is controlled by the [TRGFL AND PHSEN ] status.
VBAT 4 VBAT
D2 PHOTO
VBAT
12 PHSEN
U1 + R1 GND 100k R2 100k U2 + Comparator PHSTP
100k
R1 GND
1
PHREF
Figure 4. Basic Photo Sense Input Circuit
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NCP5080
Although it is possible to increase the photo feedback sensitivity by increasing the value of the pulldown resistor, care must be observed since such a resistor is in parallel with the internal network as depicted in Figure 4 and the input node might be too sensitive to the ambient noise. It is recommended to avoid sense resistor value above 100 kW, although that 1 MW is possible, the operation being rapidly downgraded when the resistance increases beyond this value. The PHREF voltage is setup by the external controller, in the 0.5 V to 1.5 V range, depending upon the need of the application. The internal structure includes a 500 kW (typical) resistor network, connected between PHREF pin and GND : the external reference source must support such a load and a 10 kW output impedance, or lower, is recommended to avoid uncontrolled operation. Finally, the IGBT signal will be switched OFF when the PHSEN signal reaches the PHREF reference. The function is deactivated by forcing a voltage in the 0.5 V to 1.5 V range at the PHREF pin, associated with a GND connection to the PHSEN pin.
EN Vout Ref.
When the photo sense is active and the photo sense threshold has been crossed, the photo sense feedback is internally latched and recycling the TRGFL signal (H to L) is necessary to reset the latch and start a new sequence .
Simplified Flash
The circuitry can be simplified when the application does not need the multiple flashes during the same photo sequence. In this case, the IGBT can be removed as there is no more need to dynamically switch off the xenon tube . Similarly, the photo sense becomes useless since there will be no way to control the illumination once the xenon flash has been triggered. Such a feature must be properly deactivated to avoid uncontrolled operation during a photo sequence: a simple resistor network fulfill such a requirement as depicted in Figure 6.
Vout READY
IGBT TRGFL VPH Photo transistor current Illumination = Vreference --> IGBT switched OFF
PHSEN
Figure 5. Typical Photo Sense Timings
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NCP5080
VCC GND 10k R6 U1 READY MCU EN 8 7 2 1 GND 12 10 9 R5 GND VBAT READY EN 1 TRGFL PHREF PHSEN IPK-REF AGNG NCP5080 R1 GND CI 10nF 11k R2 VHT 3.3M GND VSW PGND IGBT VFB 6 5 3 11 LDT565630T 3 GND 4 2 T1 4 MURHS160T3G XENON TUBE X1 T2 3 1 3 C4 100nF/400V 2 TRIG_FLASH GND R7 22R 2 GND 100R GND 1 220k C2 10mF/6.3V D1 1 VHT +VBAT GND C3 22mF/315V R3
Figure 6. Simplified Xenon Flash Controller
On the other hand, since it is not possible to connect the high voltage trigger pin to the controller (MCU or other digital device), the IGBT pin will be used to trig the SCR device necessary to fire the high voltage pulse as depicted in Figure 6.
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R9
11k
+VBAT GND
R10 Enable
1k
1k
R6
D5
GND Ready 10mF/6.3V D1 1 U1 8 7 EN 1 TRGFL PHREF 12 PHSEN PGND GND R7 IPK-REF IGBT VFB 11 22R 134 R12 GND 10k 11k 8 G AGNG R5 NCP5080 3 10 9 5 Vsw 6 COILCRAFT-CJ5143-AL GND 3 2 1 READY PERKIN -ELMER VBAT 4 BAS21 2 T1 4 X1 1 4 VHT D6
C2 22mF/315V
GND
C3
R3 THT 220k
+VBAT S2 EN GND ENABLE S1 TRGFL TRIGGER R11 +VBAT 100nF P1 10k
READY
3 2
1 Ns
3
Np C4 2 T2 EC3215G-X GND
76 R13
5
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C5 GND 10nF R1 12k 1R R2 VHT 3.0M GND
DEMO BOARD
Collector Q1 IGBT-CY25BAH-8F Emitter
Figure 7. Demo Board Schematic Diagram
NCP5080
GND GND J3 PHOTOEN 3 1 2 R4 SHB410 +VBAT GND Q2
GND
10
C1 10k 10k
NCP5080
Figure 8. Output Capacitor Recharge Cycle
Figure 9. Xenon Tube Discharge Current
Figure 10. Recycling VOUT Slope and Battery Input Current with Ipeak = 1.5 A
Figure 11. Recycling VOUT Slope and Battery Input Current with Ipeak = 750 mA
TRGFL: Trigger Flash pulse PHREF: photo sense reference voltage ( provided by the external circuit) PHSEN: photo sense input voltage ( provided by the photo transistor sensor )
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PACKAGE DIMENSIONS
LLGA12 CASE 513AD-01 ISSUE A
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.50 0.60 0.00 0.05 0.20 0.30 3.00 BSC 2.75 2.85 3.00 BSC 1.65 1.75 0.50 BSC 0.20 --0.35 0.45
2X
0.15 C
2X
0.15 C
0.10 C A
12X
0.08 C A1 SIDE VIEW C
SEATING PLANE
12X
K
12X
L
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CCCC CCCC CCCC
D2
1 12
PIN ONE REFERENCE
E
TOP VIEW
SOLDERING FOOTPRINT*
3.30
12X 1
0.56
6
e 0.40 0.25 PITCH 2.78
E2
11X 7 12X
b BOTTOM VIEW
0.10 C A B 0.05 C
NOTE 3
0.28
1.73
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP5080/D

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